Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (RRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.
Some memory devices include memory arrays exhibiting memory cells arranged in a cross-point architecture including conductive lines (e.g., access lines, such as word lines) extending perpendicular (e.g., orthogonal) to additional conductive lines (e.g., data lines, such as bit lines). The memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells. Select devices can be used to select particular memory cells of a memory array.
Challenges related to memory device fabrication include decreasing the size of a memory device, increasing the storage density of a memory device, and reducing fabrication costs. For example, fabricating 3D cross-point memory arrays often requires forming high aspect ratio memory cells from stacks of materials. Frequently, materials that are sensitive to downstream processing conditions are present in the stacks. For example, 3D cross-point memory cells may include materials, such as chalcogenide materials, carbon-containing materials, and other sensitive materials, that may be damaged at the temperatures used during conventional semiconductor fabrication processes and/or that may undesirably react with various materials (e.g., etchants, oxidizers) used during downstream processing. For instance, chalcogenide materials in the stacks may volatilize during conventional deposition techniques, causing delamination of the stack materials. To protect the stacks, liner materials have been formed over the materials of the stack before subsequent processing acts are conducted. Unfortunately, conventional liner materials and conventional liner material systems can damage the materials of the stack during formation, can suffer from one or more of poor adhesion to the different materials of the stack, can adversely interact the additional materials formed thereover during subsequent processing acts, and/or can hinder the efficacy of subsequent processing acts (e.g., subsequent material removal processes, such as subsequent chemical-mechanical planarization acts).
A need, therefore, exists for new memory structures, such as cross-point memory structures, including liner materials overlying memory cells, as well as for semiconductor devices (e.g., memory devices) and electronic systems including the memory structures, and methods of forming the memory structures that overcome one or more (e.g., all) of the aforementioned problems of conventional memory structures, conventional semiconductor devices, conventional electronic systems, and conventional methods of forming memory structures.